1. Field of the Invention
This invention relates generally to chemical mechanical planarization or polishing tools and, more particularly, to a method and apparatus of in-line oxide thickness determination subsequent to chemical mechanical polishing of a semiconductor wafer.
2. Discussion of the Related Art
In semiconductor device manufacturing of very large scale integrated (VLSI) circuits, extremely small electronic devices are formed in separate dies on a thin, flat semiconductor wafer. In general, various materials which are either conductive, insulating, or semiconducting are utilized in the fabrication of integrated circuitry on semiconductor wafers. These materials are patterned, doped with impurities, or deposited in layers by various processes to form integrated circuits. VLSI integrated circuits include patterned metal layers which are generally covered with dielectric materials, such as oxide, followed by a subsequent metalization, etc. The semiconductor wafers thus contain metalization layers and interlevel dielectrics.
Increasing circuitry miniaturization and a corresponding increase in density has resulted in a high degree of varying topography being created on an outer wafer surface during fabrication. It is often necessary to planarize a wafer surface having varying topography to provide a substantially flat planar surface. One such planarization process known in the art is chemical-mechanical polishing (CMP).
Chemical mechanical polishing or planarization has been widely used in the semiconductor industry for smoothing, polishing or planarizing coating or layers on the surface of semiconductor wafers. This process has been used to achieve the planarization, the controlled reduction in thickness, or even the complete removal of such layers which may include, for example, an oxide on the surface of the semiconductor wafer. Apparatus for such chemical mechanical polishing process is well known and used in the semiconductor industry and is currently commercially available.
Briefly, the chemical mechanical polishing process requires that a workpiece be held, with the desired coated surface face down, on a polishing pad supported on a rotating table, in the presence of an abrasive slurry. A chemical mechanical polishing machine can include a single rotating polishing plate and a smaller diameter rotating wafer carrier to which a wafer (or wafers) is (are) mounted. The wafer carrier is held above the polishing plate, either in a stationary fixed position or oscillating back and forth in a predetermined path, while both polishing plate and wafer carrier are rotated about their respective center axes. A slurry, consisting of an abrasive suspension with or without an etching reagent, is fed onto the polishing plate during polishing of the wafer. The slurry, also referred to as a carrier liquid, can be selected to include an etchant for the coating being planarized and for not substantially attacking other materials involved in the process. The slurry is further fed between the polishing plates to polish and flush away the material removed from the semiconductor wafer.
Referring now briefly to FIG. 1, an example of the formation of a dielectric 10 is shown above two devices in the fabrication of a high performance VLSI circuit 12. The dashed line is representative of the non-planar topology of the dielectric material 10 subsequent to its formation and/or deposition upon the surface of the wafer 14. Bumps 16 are noted in the top surface 18 of the dielectric layer 10, layer 10 having, for example, a nominal thickness on the order of 10,500 .ANG. as indicated by arrow 20. The dielectric layer 10 is planarized to a desired level 22 above the devices, layer 10 then having a desired nominal thickness on the order of 6,500.+-.500 .ANG., as indicated by arrow 24. Planarization may be achieved upon polishing back, using CMP, to the level 22 as shown by the solid line. FIG. 2, is representative of an example of a subsequent manufacturing step using the substrate of FIG. 1, including a local interconnect metalization M0 in the first dielectric layer 10, an intermediate dielectric layer 30 having vias 32 formed therein, and a first interconnect metalization layer M1. A dielectric layer 34 is formed upon the first metalization layer M1, wherein the dashed line is representative of the non-planar topology of the dielectric material above the first metalization layer M1. Bumps 36 are noted in the top surface 38 of the dielectric layer 34, layer 34 having, for example, a nominal thickness on the order of 20,500 .ANG. as indicated by arrow 40. The dielectric layer 34 may then be planarized using CMP to a desired level 42 above the top of the first metalization layer M1, layer 34 then having a desired nominal thickness on the order of 9,000.+-.500 .ANG., as indicated by arrow 44.
A persistent difficulty in the fabrication of VLSI wafers is the inability to determine when a required thickness or endpoint has been reached during a dielectric polishing step. one method of determining the required thickness or CMP endpoint is by using estimated CMP rates and times. CMP rates vary considerably with time however, due to changes in polishing pad characteristics, for example. Frequent stops are required in the fabrication process for ex-situ optical thickness measurements. With ex-situ thickness measurements, the method is extremely time consuming and highly undesirable since operators must handle, unload, and dry each wafer after polish before making the ex-situ thickness measurement. Process throughput is thereby reduced and product yields are lowered. A more precise CMP endpoint detection method and apparatus is desired.
It would be desirable to provide a solution to the problem of how to accurately determine a thickness of an interlevel dielectric remaining above a patterned VLSI wafer, post chem-mech planarization, without an undesirable extra handling, unloading and drying of the wafer. Furthermore, a thickness determination method and apparatus which makes use of low voltage operation and is compatible for use in the VLSI fabrication of low voltage (i.e., less than one-half volt) silicon junction devices is also desired. In addition, there remains a continuing need in the semiconductor fabrication art for an apparatus and method for accurately and efficiently detecting and monitoring dielectric thickness during a polishing sequence of a chemical-mechanical planarization process.